Function Block Diagram Symbols: Every Standard Block and What Its Pins Mean

Every function block diagram is built from the same small vocabulary. Once you can read about two dozen standard blocks, and the handful of marks drawn on their pins, you can read FBD on any PLC brand. Siemens draws an AND as &, Rockwell spells instruction names out, CODESYS follows IEC 61131-3 closely, but the blocks and their pins are the same. This page is the reference: each standard symbol, what every pin means, and the mistake people make with it.

If you are new to FBD, start with What Is a Function Block Diagram? for the idea, then the FBD tutorial for how networks execute. Come back here when a block on the screen needs decoding.

The marks that appear on any block

Mark	Where	Meaning
Type name	Inside the box, top	What the block does: AND, TON, CTU, ADD
Instance name	Above the box	Which copy of a block with memory this is (FillDelay, BottleCount)
Input pins	Left edge	Values the block reads this scan
Output pins	Right edge	Values it produces this scan
Small circle on a pin	Input or output	Negation: the signal is inverted at that pin
EN / ENO	Top corners (some vendors)	Execute only when EN is TRUE; ENO passes "it ran" along
Variable box	Ends of a network	A program variable feeding the network, or the one it assigns

Two kinds of block look alike but behave differently. Functions (AND, ADD, GT) have no memory: the same inputs always give the same output. Function blocks (TON, CTU, SR, R_TRIG) keep state between scans, which is why they always carry an instance name. Two timers need two instances, never one shared.

Bit logic: AND, OR, XOR, NOT

Block	Inputs	Output	TRUE when
AND (&)	IN1 … INn (BOOL)	OUT	every input is TRUE
OR (>=1)	IN1 … INn	OUT	at least one input is TRUE
XOR (=1)	IN1, IN2	OUT	exactly one input is TRUE
NOT	IN	OUT	the input is FALSE

Most editors let you stretch AND and OR to more inputs. A negation circle on an input does the job of a NOT block. A normally-closed stop button feeding an AND through a circled pin is the FBD form of the ladder -|/|- contact. The mistake to avoid is negating twice. A stop button that is wired normally closed already reads TRUE while healthy, so the logic wants the plain signal, not a circled pin.

Timers: TON, TOF, TP

All three IEC timers share one interface:

Pin	Direction	Type	Meaning
IN	input	BOOL	start condition
PT	input	TIME	preset, e.g. T#5s
Q	output	BOOL	timer output
ET	output	TIME	elapsed time

• TON (on-delay): Q turns on once IN has been TRUE for PT, and off the moment IN drops. Use it for "the bottle must be in place for 1 second before the valve opens".
• TOF (off-delay): Q turns on with IN and stays on for PT after IN drops. Use it for "run the fan for 2 minutes after the heater stops".
• TP (pulse): a rising IN produces a Q pulse exactly PT long, and retriggering during the pulse does nothing. Use it for "fire the cutter for 500 ms".

The usual mistake is expecting a TON to hold. If IN flickers off for one scan, ET resets to zero and the delay starts over. Timing details are in PLC Timers Explained.

Counters: CTU, CTD, CTUD

Block	Inputs	Outputs	Behaviour
CTU	CU (count), R / RESET, PV (preset)	Q, CV	CV +1 on each rising edge of CU; Q when CV >= PV; R clears
CTD	CD, LD (load), PV	Q, CV	LD loads PV; CV −1 per edge of CD; Q when CV <= 0
CTUD	CU, CD, R, LD, PV	QU, QD, CV	both directions, one count

Counters count edges, not levels: a button held for half a second is one count, not fifty. The edge detection is built into the CU pin. A retentive counter, one that keeps its count through a power cut, is the same block declared in a VAR RETAIN section. The block symbol does not change; good editors mark it with an R. More in PLC Counters Explained.

Edges: R_TRIG and F_TRIG

Block	Input	Output	TRUE for one scan when
R_TRIG	CLK	Q	CLK goes FALSE → TRUE
F_TRIG	CLK	Q	CLK goes TRUE → FALSE

Use an edge block whenever an action must happen once per event: count a bottle once, latch a fault once, advance a sequence step once. Feeding a level signal straight into something that should happen once is the most common FBD bug.

Bistables: SR and RS

Block	Inputs	Output	When both inputs are TRUE
SR (set-dominant)	S1 (SET1), R (RESET)	Q1	Q1 is TRUE: set wins
RS (reset-dominant)	S (SET), R1 (RESET1)	Q1	Q1 is FALSE: reset wins

The pin with the 1 is the dominant one. The IEC standard names the pins S1/R and S/R1; CODESYS-style editors write SET1/RESET and SET/RESET1. Pick by asking what must happen if both conditions are true at once. A run latch wants stop to win, so it is an RS. An alarm that must not be cleared while its cause is present can be an SR.

Comparison

Block	Inputs	Output TRUE when
GT (>)	IN1, IN2	IN1 > IN2
GE (>=)	IN1, IN2	IN1 >= IN2
EQ (=)	IN1, IN2	IN1 = IN2
NE (<>)	IN1, IN2	IN1 <> IN2
LE (<=)	IN1, IN2	IN1 <= IN2
LT (<)	IN1, IN2	IN1 < IN2

Comparators turn numbers into BOOLs. A level alarm is GT with the level on IN1 and the limit on IN2. Avoid EQ on REAL values: an analogue reading is almost never exactly equal to anything, so compare with GE/LE or a small band.

Arithmetic and selection

Block	Inputs	Output	Notes
ADD, SUB, MUL, DIV	IN1, IN2 (ADD/MUL extensible)	OUT	integer DIV truncates; a divide by zero is a fault
MOD	IN1, IN2	OUT	remainder
MOVE	IN	OUT	copies a value; with EN it copies only when enabled
SEL	G, IN0, IN1	OUT	IN0 when G is FALSE, IN1 when TRUE
MAX, MIN	IN1 … INn	OUT	the largest or smallest input
LIMIT	MN, IN, MX	OUT	IN clamped between MN and MX
MUX	K, IN0 … INn	OUT	the input selected by the number K

LIMIT is the block people forget. Clamping a setpoint before it reaches an output is one block in FBD and several rungs in ladder.

Reading a whole network

Put the vocabulary together and a network reads left to right like a sentence. Take Start and Run into an OR, that OR and a healthy Stop into an AND, and the AND into Run: a seal-in. Then Run and BottleSensor into an AND, into a TON with PT = T#1s, and its Q sets the FillValve latch: the valve opens once a bottle has been in place for a second. Nothing on that page is vendor-specific.

How PLC-Ladder draws these blocks

PLC-Ladder shows every program as Ladder and as FBD from the same compiled logic, so you can check a block against its rung. The blocks it compiles today are bit logic, TON, CTU/CTD, R_TRIG/F_TRIG, SR/RS, the comparators, arithmetic, LIMIT/MIN/MAX and your own function blocks. TOF, TP, CTUD and MUX are not supported yet, and the compiler says so with a line number rather than guessing. Retentive blocks carry a "Rem" mark in the FBD view. Every diagram runs in the simulator, so you can toggle the inputs and watch each pin change.

To see the examples above as working circuits, open FBD Programming Examples: eight networks, explained block by block.