Function Block Diagram (FBD) in PLC Programming: The Complete Tutorial

Function Block Diagram (FBD) is one of the five PLC programming languages defined by IEC 61131-3, and after ladder logic it is the one you will meet most often on real machines. Instead of rungs, contacts and coils, an FBD program is a network of rectangular blocks connected by wires: signals flow in from the left, pass through logic, timers, counters and math, and come out on the right as commands to your outputs. This tutorial covers everything you need to read and write FBD confidently — what the blocks and pins mean, how the PLC decides execution order, and when FBD is the better choice than ladder.

What Is a Function Block Diagram in PLC Programming?

An FBD program describes logic as a signal-flow graph. Three kinds of elements appear on the page:

Blocks. Each rectangle performs one operation. Simple ones are functions — AND, OR, ADD, GT — which have no memory: the same inputs always produce the same output. The more interesting ones are function blocks — TON timers, CTU counters, SR latches, PID loops — which keep internal state between scans and therefore need an instance name (like MotorDelay : TON) so the PLC knows which timer's elapsed time is which.

Wires (connections). Lines carry values from an output pin of one block to an input pin of another. A wire has a data type: a BOOL wire carries TRUE/FALSE, an INT wire carries a number, a TIME wire carries a duration. You cannot legally connect an INT output to a BOOL input — the editor (or the compiler) will stop you, and that type checking is one of FBD's quiet advantages over sprawling ladder rungs full of compare instructions.

Pins (formal parameters). Inputs enter on the block's left edge, outputs leave on the right. A TON timer, for example, has IN (start condition) and PT (preset time) on the left, Q (done) and ET (elapsed time) on the right. Some vendors add EN/ENO pins on math and move blocks: if EN is FALSE the block simply doesn't execute that scan, and ENO passes the enable along the chain.

A minimal network — start/stop seal-in for a motor — looks like this in FBD: the Start pushbutton and the running feedback go into an OR block, its output and the (normally-closed) Stop signal go into an AND block, and the AND output drives the Motor coil. Exactly the logic every electrician knows from ladder, drawn as gates.

How FBD Executes: Networks, Scan Cycle and Execution Order

FBD does not execute "all at once." A PLC runs a scan cycle: read inputs, execute the program top to bottom, write outputs, repeat — typically every few milliseconds. Within an FBD program:

Networks execute in order, first network first. A network is one connected group of blocks; most editors number them.
Within a network, blocks execute in data-flow order: a block runs only after all the blocks feeding its inputs have run. Signals effectively move left to right.
Feedback loops are the exception. If you wire a block's output back toward its own input (the classic seal-in does this), the loop must be broken somewhere by a variable, and that value is the one computed on the previous scan. This is why a feedback path introduces a one-scan delay — the same behavior as reading a coil earlier in a ladder program than it is written.

Two practical consequences follow. First, order your networks the way the signal flows through the machine: compute permissives before the logic that uses them, or you'll chase one-scan-late bugs. Second, never program a counter's CU pin from a level signal. A PLC scanning at 10 ms will see a half-second button press as ~50 TRUE scans; without an edge-detect block (R_TRIG) in front, your counter jumps by 50 per press. In FBD, dropping an R_TRIG between the button and the counter makes the fix visible on the page.

Every FBD network has a direct Structured Text equivalent, which is a useful way to check your reading of a diagram. The seal-in plus a 5-second run-delay timer:

PROGRAM MotorControl
VAR
    Start, Stop, Motor : BOOL;
    RunDelay : TON;          (* instance of a timer function block *)
    Pump : BOOL;
END_VAR

Motor := (Start OR Motor) AND NOT Stop;   (* the OR/AND network *)

RunDelay(IN := Motor, PT := T#5s);        (* TON block: IN, PT in; Q, ET out *)
Pump := RunDelay.Q;                       (* wire from the timer's Q pin *)
END_PROGRAM

If you can translate a diagram into three lines like that and back, you understand its execution order.

Reading a Block: The Anatomy That's the Same Everywhere

Vendors draw FBD slightly differently — Siemens TIA Portal labels an AND gate &, Rockwell's Studio 5000 spells out instruction names, CODESYS follows the IEC standard closely — but the anatomy never changes:

Part	Where	Meaning
Type name	Top center	What the block does (TON, CTU, ADD…)
Instance name	Above the block	Which copy of a stateful block this is
Input pins	Left edge	Values the block consumes this scan
Output pins	Right edge	Values it produces this scan
Negation circle	On a BOOL pin	Inverts the signal at that pin
EN / ENO	Top corners (some vendors)	Conditional execution and its pass-through

Learn the standard set — AND/OR/NOT, TON/TOF/TP, CTU/CTD, R_TRIG/F_TRIG, SR/RS, MOVE, the comparators GT/GE/EQ — and you can read 90% of FBD programs on any brand. (We cover every pin of every one of these in Function Block Diagram Symbols: Every Standard Block and What Its Pins Mean.)

FBD vs Ladder Logic: When to Use Which

FBD and ladder compile to the same thing; the question is which one makes a given piece of logic readable. A fair rule of thumb:

Choose ladder when the logic is interlocks. Start/stop circuits, permissive chains, safety-adjacent AND/OR conditions — electricians and maintenance techs read rungs fluently at 2 a.m., and series-contacts-equal-AND is hard to beat.

Choose FBD when the logic is signal processing. Anything with a chain of math, scaling, filtering, PID, analog alarms with hysteresis, or several timers feeding each other becomes a wall of MOV/CPT/CMP instructions in ladder but reads left-to-right naturally as blocks. Continuous-process industries lean FBD for exactly this reason.

Choose Structured Text when the logic is algorithmic — loops, arrays, string handling — because neither graphical language loops well.

Real programs mix languages: ladder for the motor interlocks, FBD for the analog section, ST inside a custom function block. IEC 61131-3 explicitly allows this, and it is the approach we'd recommend rather than loyalty to any single language. The deeper point — that these are two notations for one underlying logic — is something you can prove to yourself in about a minute: in the PLC-Ladder simulator, draw the seal-in above as FBD, flip the same program to the ladder view, and toggle the Start input while watching both light up together. Nothing sells the equivalence like seeing the same scan animate both diagrams.

Common FBD Mistakes to Avoid

Reusing one timer instance in two places. Two networks calling RunDelay are sharing one elapsed-time register and will fight. One stateful job, one instance.
Counting on a level instead of an edge. Put R_TRIG in front of CU. Always.
Unbroken feedback loops. Break the loop with a named variable so the one-scan delay is explicit and intentional.
Ignoring ENO. In EN/ENO vendors, a divide-by-zero drops ENO; chain it, or downstream blocks compute on stale data.
Monster networks. One network per output, same as the one-rung-per-coil discipline in ladder. Ten small networks beat one heroic diagram.

Where to Go Next

You now have the whole skeleton: blocks with typed pins, wires that carry values, networks that scan in order, feedback that costs one scan. To make it concrete, work through FBD Programming Examples: 8 Real Circuits Explained Block by Block, and if you're still weighing languages, Ladder Logic for Beginners shows the same foundational circuits from the rung side. Open either one next to a simulator and build as you read — FBD is a language you learn through your hands. Visit to PLC-Ladder.com