What Is a Function Block Diagram (FBD)? Ladder's Sibling, Explained
The IEC 61131-3 function block diagram explained: blocks, pins and wires flowing left to right, how it relates to ladder logic, and where each view wins.
If ladder logic is the PLC language technicians grew up with, the function block diagram is the one control engineers reach for when the problem stops being about contacts. Both are graphical languages in IEC 61131-3, both describe the same scan-by-scan behaviour, and a lot of real programs are a mix. Here is what an FBD actually is, what it is good at, and why we draw one for every program alongside the ladder.
Blocks, pins, wires
A function block diagram draws logic as boxes connected by lines. Each box is a function or a function block: an AND gate, an OR, a comparator, a TON timer, an ADD, a SQRT, or a larger block such as a PID controller or a symmetrical-components calculation. Boxes have input pins on the left and output pins on the right. Wires carry a value from one output pin to another block's input pin, and signal flows left to right across the page, from the variables that feed the network to the variable it assigns at the far right.
That is the whole grammar. A small circle on an input pin negates it. A timer block shows its IN, PT and Q pins by name. A block with memory, a timer or a latch, carries an instance name above it so you can tell two timers apart. Nothing about it is exotic; it is the wiring diagram of the logic.
The same logic two ways
Take an under-frequency stage with a voltage check and a two-second delay.
Stage1 := GridFreq < 49.5 AND BusVoltage > 0.8 AND NOT Blocked;
Stage1Delay(IN := Stage1, PT := T#2s);
Trip1 := Stage1Delay.Q;
In ladder, the first line is one rung: two comparison boxes and a normally-closed contact in series, driving the Stage1 coil. In FBD, the same line is two comparator blocks and a Blocked variable feeding a three-input AND whose output wire lands on Stage1 :=. The timer line is a TON block with Stage1 on IN and T#2s on PT; the trip line takes the timer's Q pin to Trip1 :=.
Neither drawing is more correct. They are two projections of one behaviour, and a reader who knows one can learn the other in an afternoon.
Where FBD is the better view
Ladder is unbeatable for boolean interlocks, because series and parallel contacts are AND and OR and everybody on the floor can read them. It gets awkward as soon as numbers appear. A rung that computes ABS(GridFreq - 50.0) has nowhere natural to put the arithmetic, so it ends up in a compute box with the expression as text, which is honest but not graphical.
FBD handles that case natively: a SUB block, an ABS block, a wire between them, live values written on the wires while the simulator runs. For anything with signal processing, scaling, filtering, phasor math or power calculations, the block diagram shows the data flow and the ladder shows a box. That is why our math networks are FBD-first: the ladder view still renders them, but the FBD is where you check them.
The other place FBD earns its keep is reuse. A library block such as SYM_COMP, which turns three phase voltages into positive-, negative- and zero-sequence components, is one glyph with labelled pins. Click it and it expands to show the arithmetic inside; collapse it and the diagram reads at the level of the engineering. Ladder can show the call as a single rung, but not the internals.
Where ladder still wins
Sequences of set and reset, permissives, start/stop seal-ins and anything a maintenance technician will troubleshoot at two in the morning. The floor reads rungs. A ladder printout on the cabinet door is still the fastest way to find out why a conveyor did not start, and an FBD of the same logic would take longer to trace. Good practice is to keep interlocks in ladder and computation in blocks, and most vendor tools let you mix them per program section.
Reading an FBD during simulation
The habit that helps most is to read wires, not blocks. A boolean wire is either carrying power or not; when the simulator runs, ours turns green and animates while it is true. A numeric wire carries a value, printed beside it. Start at the far right, at the assignment you care about, and walk left along the wires asking "why is this value what it is". The first block whose inputs do not explain its output is your bug. It is the same technique as tracing a rung from the coil back to the rails, applied to a different drawing.
One model, two drawings
In our tool the ladder and the FBD are generated from the same compiled model, never from each other and never by hand. When the compiler accepts a program it produces one intermediate representation; the ladder renderer and the FBD converter both read it. That has a consequence we care about more than the pictures: the two views cannot disagree. Force an input in the rail while looking at the FBD, switch to the ladder, and the same coil is energised, because there is only one simulation underneath.
If you have only ever seen ladder, the fastest way to learn FBD is to look at logic you already understand in both views at once. Write a seal-in, watch it latch as a rung, then flip the tab and watch the same latch as an SR block with the same two inputs. After a few of those, the block diagram stops being a foreign language and becomes what it is: the same logic, drawn for a different question.
Try it: describe your logic in plain English at PLC-Ladder, and switch between the Ladder and FBD tabs to see both views of the same verified program.